期刊文献+

电容误差平均技术在流水线ADC中的应用 被引量:1

Application of Capacitor Error-averaging Techniques in Pipeline ADC
下载PDF
导出
摘要 随着流水线ADC精度的不断提高,其转换器性能受到各种电路非线性的严重影响。电容失配是引起非线性的一种主要因素。实践表明,电容误差平均技术是消除失配误差的一种有效途径。介绍几种重要的电容误差平均方法的原理和工作方式,并指出各自存在的优缺点。最后对误差校准技术的发展趋势进行分析与展望。 With the increasing resolution of pipeline ADC, the performance of such converters is badly affected by various circuit nonlinearities. Capacitor mismatch is one of the main sources of nonlinearities. It has been proved that one efficient approach to treat mismatch error is Capacitor Error- Averaging (CEA). In this paper, the theoretics and operational styles of several significant capacitor error-averaging calibration methods are introduced. Their respective flaws are also indicated. In the end, the development trend of error calibration techniques is illuminated.
出处 《现代电子技术》 2008年第4期15-17,20,共4页 Modern Electronics Technique
关键词 流水线ADC 电容误差平均 电容交换 误差校准 pipeline ADC capacitor error - averaging capacitors exchange error calibration
  • 相关文献

参考文献9

  • 1Bang- Sup Song,Tompsett M,Lakshmikumar K. A 12 -bit 1 - MSample/s Capacitor Error - Averaging Pipelined A/D Converter[J]. IEEE Journal of Solid - State Circuits, 1988, 23(6):1 324-1 333.
  • 2Hsin- Shu Chen,Bang- Sup Song,Kantilal Bacrania. A 14- b 20 - Msamples/s Cmos Pipelined ADC[J]. IEEE Journal of Solid- State Circuits,2001,36(6) :997 - 1001.
  • 3Chiu Y. Inherently Linear Capacitor Error - Averaging Techniques for Pipelined A/D Conversion[J]. IEEE Trans. Circuits Syst. Ⅱ ,2000,47(3) :229 - 232.
  • 4Chiu Y,Paul R Gray,Nikolic B. A 14 - b 12 - MS/s Cmos Pipeline ADC With Over 100 - dB SFDR[J]. IEEE Journal of Solid- State Circuits,2004,39(12) :2139 - 2151.
  • 5李福乐,李冬梅,张春,王志华.流水线结构模数转换器电容的误差平均技术[J].清华大学学报(自然科学版),2003,43(1):63-66. 被引量:1
  • 6李福乐,王红梅,李冬梅,王志华.一种用于流水线模数转换器的电容失配校准方法[J].Journal of Semiconductors,2005,26(9):1838-1842. 被引量:2
  • 7Bernal O, Bony F, Laquerre P, et al. Digitally Self - Calibrated Pipelined Analog - to - Digital Converter [A]. IEEE IMTC Proceedings, Sorrento, Italia, 2006.
  • 8Karanicolas Andrew N, Hae- Seung Lee,Kantilal L. Bacrania. A 15 - b 1 - Msample/s Digitally Self - Calibrated Pipeline ADC [J]. IEEE Journal of Solid- State Circuits, 1993, 28(12):1 207-1 215.
  • 9Alma Deli'c- Ibuki'c,Donald M Hummels. Continuous Digital Calibration of Pipeline A/D Converters[J]. IEEE Transactions on Instrumentation and Measurement, 2006, 55 (4):1 175-1 185.

二级参考文献11

  • 1Chen H S,Bacrania K,Song B S. A 14b 20Msample/s CMOS pipelined ADC. ISSCC Dig Tech Papers, San Francisco, 2000:46.
  • 2Karanicolas A N, Lee H S, Bacrania K L. A 15-b 1-Msample/s digitally self-calibration pipeline ADC. IEEE J Solid-State Circuits,1993,28(12) :1207.
  • 3Mayes M K, Chin S W. A 200mW, 1Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller. IEEE J Solid-State Circuits, 1996,31 (12) : 1862.
  • 4Moon U K, Song B S. Background digital calibration techniques for pipelined ADC ' s. IEEE Trans Circuits Syst Ⅱ ,1997,44(2) : 102.
  • 5Song B S, Tompsett M F, Lakshmikumar K R. A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter. IEEE J Solid-State Circuits,1988,23(6):1324.
  • 6Lin Y M,Kim B,Gray P R. A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-um CMOS [J]. IEEE J Solid-State Circuits,1991,26(4): 628-636.
  • 7Mayes M K,Chin S W. A 200 mW,1 M sample/s,16-b pipelined A/D converter with on-chip 32-b microcontroller [J]. IEEE J Solid-State Circuits,1996,31(12): 1862-1872.
  • 8Moon U K,Song B S. Background digital calibration techniques for pipelined ADC's [J]. IEEE Trans Circuits Syst II,1997,44(2): 102-109.
  • 9Song B S,Tompsett M F,Lakshmikumar K R. A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter [J]. IEEE J Solid-State Circuits,1988,23(6): 1324-1333.
  • 10Chen H S,Bacrania K,Song B S. A 14 b 20 M sample/s CMOS pipelined ADC [A]. ISSCC Dig Tech Papers [C],San Francisco IEEE,2000. 46-47.

共引文献1

同被引文献5

  • 1李福乐,王红梅,李冬梅,王志华.一种用于流水线模数转换器的电容失配校准方法[J].Journal of Semiconductors,2005,26(9):1838-1842. 被引量:2
  • 2POTANIN V , POTANIN V Y. Li-ion battery charger with three-parameter regulation loop [ C ]. IEEE 36^th Power Electronics Specialists Conf,2005:2836-2840.
  • 3CHEN HSIN-SHU, SONG BAMG-SUP. Kantilal Bacrania, A 14-b 20-Msample/s Cmos Pipelined ADC [ J ]. IEEE Journal of Solid-State Circuits, 2001,36 ( 6 ) : 997- 1001.
  • 4JACOB BAKER R. CMOS: Mixed-Signal Circuit Design [ M ]. Wiley-IEEE Press,2002:314-347.
  • 5SONG BANG-SUP, TOMPSEqT M, LAKSHMIKUMAR K. A 12-bit-MSample/s Capacitor Error-Averaging Pipelined A/D Converter [ J ]. IEEE Journal of Solid-State Circuits, 1988,23 (6) : 1324-1333.

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部