解决CPU流水线冲突技术的设计与实现

Design and Implementation of the Techniques of Solving Pipeline Hazards in CPU

流水线是制造高性能CPU的关键技术,目前许多学者研究在FPGA上实现具有流水线结构MIPS CPU,但是在解决流水线冲突上只是通过简单的停顿流水线实现。描述一种较为通用的具有五级流水线的MIPS CPU结构以及其中可能发生的流水线冲突,在此基础上详细介绍解决流水线冲突的技术——数据旁路以及动态分支预测在MIPS CPU中的设计和实现,最后通过一段指令序列进行仿真验证,解决流水线冲突的技术减少指令执行所需要的时钟周期数。

Pipeline is the key implementation technique used to make fast CPU. Many developers design MIPS CPU with pipelined structure on FPGA, but they solve the problem of pipeline hazards by simply stalling pipeline. In this paper,a typical MIPS CPU with five - stage pipeline and pipeline hazards is discussed,then the methods of bypassing and dynamic branch pre diction designed in the MIPS CPU, finally the CPU is simulated through a series of instructions, the methods of solving pipeline hazards reduce clock periods of executing instructions.