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嵌入式可重构系统芯片的硬件验证平台设计 被引量:2

Design of Hardware Verification Platform for Embedded Reconfigurable SoC
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摘要 提出一种新的基于嵌入式可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法。设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性。 A new video decoding scheme based on embedded reconfigurable SoC is proposed. The software and hardware co-verification method is adopted in this scheme. And then, the corresponding hardware verification platform is designed, and the realizability of H.264 decoding algorithm on reconfigurable processor is validated.
出处 《电视技术》 北大核心 2008年第2期24-26,共3页 Video Engineering
基金 国家自然科学基金项目(60676012)
关键词 可重构处理器 系统芯片 现场可编程门阵列 软硬件协同验证 reconfigurable processor SoC FPGA hardware and software co-verification
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参考文献4

  • 1WIEGAND T, SULLIVAN J G, BJONTEGAARD G, et al. The H.264/AVC video coding standard[J]. IEEE Trans. Circuits and Systems for Video Technology, 2003,13(7):560-576.
  • 2LINDROTH T, AVESSTA N, TEUHOLA J, et al. Complexity analysis of H.264 decoder for FPGA design [C]//Proc. ICME 2006. 2006:1253-1256.
  • 3MAESTRE R, KURDAHI F J, FERNANDEZ M, et al. A framework for reconfigurable computing:task scheduling and context management-a summary[J]. IEEE Circuits and Systems Magazine, 2002,2(4): 48-51.
  • 4SINGH H, LEE M, LU G, et al. MorphoSys: an integrated reconfigurable system for data-parallel and computation intensive applications[J]. IEEE Trans. Computers, 2000,49(5):465-481.

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