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32位异步加法单元的设计与实现

Design and Implementation of a 32-Bit Asynchronous Adder
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摘要 本文采用基于宏单元的异步集成电路设计流程,实现了可用于ASIP的4段流水32位异步加法单元,并实现了其同步版本作为对比。通过仿真分析,异步加法单元性能与同步加法单元相近,在功耗方面则具有相当大的优势。 An asynchronous integrated circuit design flow based on macro cells is described. Using this design flow, a 32-bit 4-sector pipelined asynchronous adder in ASIPs is designed. Compared with the synchronous version, the asynchronous adder has the similar performance and the advantage of power consumption.
作者 李勇 阮坚 戴葵 王志英
机构地区 国防科技大学计算机学院
出处 《计算机工程与科学》 CSCD 2008年第1期123-124,128,共3页 Computer Engineering & Science
基金 国家自然科学基金资助项目(90407022)
关键词 异步加法单元 功耗 性能 设计流程 asynchronous adder power consumption performance design flow
分类号 TP333.2 [自动化与计算机技术—计算机系统结构]
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参考文献6

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二级参考文献10

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共引文献11

计算机工程与科学
2008年 第1期

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