伪准确计算的高故障容忍度冗余电路实现

High Fault Tolerance Redundant Circuit Implementation of Pseudo-Accurate Computing

本文提出了伪准确计算的概念。集成电路规模的扩大和制造工艺中不断增加的缺陷给大规模集成电路的测试和验证带来巨大的压力。针对故障容忍度(Fault Tolerance,FT)的研究是缓解测试和验证压力的有效方向。传统的错误容忍度的研究和相关的电路设计主要通过冗余的可替换电路实现无错误电路(有时只针对特定目标程序)。本文通过重新定义"准确",提出了伪准确定义的概念,并通过创新的冗余电路结构实现。示例电路为冗余伪准确反相器。本文通过伪准确反相器与三模冗余(triple-modular redundancy TMR)和双备用(two spares)等FT技术的比较,给出伪准确计算的实现原理、误差积累分析。示例电路的仿真和分析表明伪准确计算在缩减测试成本和提高系统可靠性方面有潜在的价值。

This paper forwards the concept of pseudo-accurate computing. The increasing fault in the manufacturing process of solid-state circuits is a big problem. Researches on Fault Tolerance （ FT ） are effective ways to relieve the pressure from test and verification. Traditional fault tolerance method focused on faultless circuit or relative faultless （ to target application ）. This paper redefine ＂accurate＂ do the computation with pseudo-accurate result. The sample circuit implementation of a pseudo-accurate inverter is given. By the comparison among pseudo-accurate inverter, triple-modular redundancy （ TMR ） and two spares technique, the principle and error analysis of pseudo-accurate computing are given. The simulation and analysis of the sample circuit shows that pseudo-accurate computing has potential benefit in reducing cost of testing and increase system reliability.