SOI CMOS器件研究

Study on SOI CMOS Devices

利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。

A 0.35 μm fully-depleted silicon-on-insulator （SOI） complementary metal-oxide-semiconductor （CMOS） device was fabricated by using dual-polysilicon-gate technology,raised source/drain and lowly doped source/drain （LDD） structure.The divices are good performance and small dimension, and it can prevent from drain breakdown,suppresse the short-channel effect （SCE） and draln-inducedbarrier-lowing effect （DIBL） .The current drivability and reducing series resistance in raised source/drain.A was increased due to increasing thickness size 101 stages ring oscillator was designed, and the circuit was analysed. Based on the oscillating wave figure of the circuit with 3V supply voltage, the delay of per stage is 45 ps, which is far less than that of bulk silicon CMOS.