一种双采样10位50MS／s采样保持电路的设计

Design of a Double-Sampling 10-Bit 50MS/s Sample-and-Hold Circuit

介绍了一种可以进行双采样的10位50 MS/s采样保持电路。该电路采用SMIC 0.25μm标准数字CMOS工艺进行设计。基于BSIM3V3 Spice模型,采用Hspice对整个电路进行了仿真。结果表明,电路在工作于50 MS/s、输入信号频率为25 MHz时,输出信号的SNDR为62.1dB,整个电路的功耗仅为8.41 mW。

A double-sampling 10-bit 50 MS/s sample-and-hold circuit is presented. The S/H circuit is realized in SMIC＇s 0. 25 μm standard CMOS process. Based on BSIM3V3 Spice model, the whole circuit is simulated with Hspice. Results show that, for a single power supply of 2.5 V, the circuit achieves an SNDR of 62.1 dB at Nyquist frequency, with a static power dissipation of 8.41 mW.