一种新型单电子-MOS晶体管混合的半加器电路

A Novel Half Adder Circuit Using Hybrid Single Electron and MOS Transistors

基于单电子晶体管的I-V特性和MOS晶体管的逻辑电路设计思想,提出了1个单电子晶体管和MOS晶体管混合的反相器电路,进而推导出其它基本逻辑门电路,并最终实现了一个半加器电路。通过比较单电子晶体管和MOS晶体管两者的混合与纯CMOS晶体管实现的半加器电路,元器件数目得到了减少,电路结构得到简化,且电路的静态功耗降低。SPICE验证了电路设计的正确性。

Based on I - V characteristics of single - electron transistor and the idea of MOS digital circuit design, an inverter using the single - electro and MOS transistors is proposed and some other logic gate circuits are educed. Finally a novel half adder circuit is realized using these logic eireuits. The half adder circuit, in comparison with the pure CMOS circuit, has the advantages that the number of transistor is decreased, the structure of the circuit is predigested, and the total static power consumption is reduced. The accuracy of the circuit is validated by SPICE.