高速除法器设计及ASIC实现

High Speed Divider and ASIC Implementation

为提高除法计算的速度,提出了新的基-16算法的高速除法器算法,并以专用集成电路设计方法实现。与MIPS处理器中使用的除法器相比,电路最大延迟减少了27%,计算所需时钟周期数减少了68%,速度性能改善了77%左右。给出了电路的其他性能指标。该电路适用于对运算速度要求非常高的场合。

In order to improve the speed of division, a novel algorithm of radix-16 high speed divider and its ASIC implementation are presented. Compared with the divider used in the MIPS core processor, the radix-16 high speed divider can decrease the maximum circuit delay by 27%, decrease the clock cycles needed in one computation by 68%, and improves circuits speed by 77 %. The paper gives other properties of the circuits. This circuit is very suitable for high speed applications.