FFT处理器的一种扫描内建自测试方案

Scan-based built-in self-test scheme for FFT processor

对FFT处理器提出了一种采用扫描的内建自测试方案。该方案充分利用FFT结构上的规则性,采用扫描的可测性设计,不需要对处理器内部基本功能单元作任何更改,且测试序列生成和响应压缩都可通过对已有功能模块如累加器的复用来完成。通过将系统已有流水线寄存器构成扫描链且通过扫描链的可重构,不仅进一步简化了测试设计要求,而且减少了硬件成本和系统性能占用,同时还具有测试向量少、故障覆盖率高的优点。

A scan-based design for testability scheme is proposed for built-in self-test of pipelined FFT processor utilizing its highly regular architecture. It needs no modification of the basic cells. The generation of test vectors and compaction of test responses can be performed by available accumulators. By reconfiguring of scan chains with existing pipelined registers, this scheme can further reduce hardware overhead and performance degradation. It also has the advantages of short test sequences and high fault coverage.