逻辑内建自测试高故障覆盖率设计

High Fault Coverage Design of Logic Built-In-Self-Test

基于扫描的可测性设计技术需要大量空间存储测试矢量,并且难以实现全速测试,随着芯片规模越来越大,频率越来越高,其测试成本也将越来越高,逻辑内建自测试(Logic Built-In-Self-Test,LBIST)技术以其简单的硬件实现和较小的设计开销开始被业界广泛使用,但该技术也存在覆盖率较低的问题,主要原因在于:一是线性反馈移位寄存器(Linear Feedback Shift Register,LFSR)产生的伪随机矢量的空间相关性;二是电路结构上对伪随机矢量的抵抗性;针对这两种原因给出了一些改善的方法,从而达到提高故障覆盖率的目的,为实际设计提供借鉴。

Scan test, as one type of design - for- test. needs large size of memory to restore test patterns, and it is difficult to proceed at - speed lest. As the size and frequency of chips increased, the cos,, of scan tesl will increase rapidly. So nov,, logic buih-in self lesl has bcen widely adopled for its simph hardware implernentation and small design effort. But its fault coverage front randomly - generated lest pauerns is nmch lower thau thai from ATPG. There are two reasons of that. The first reason is the space correlativity of Iesl patterns generated by Linear Feedback Shift Register, and the second reason is the resistance lo pseudo- random lest patterns. Here we present several novel high fauh coverage LBIST design techniques, which can give directions in real design.