基于部分向量复用和变游程编码的二级SoC测试压缩

Two level core test compression based on partial test vector reuse and VRL coding

提出了一种适用于基于核的SoC测试数据压缩的新方法,先将不同待测核对应的测试集中的测试向量部分重叠起来,形成一个重叠向量,对这个重叠向量进行变游程编码(VRL),以进一步压缩测试向量。由于测试应用时间与重叠向量的长度成正比,而重叠向量的长度要远小于原始测试向量的长度总和,从而减少了测试时间。变游程编码最大化了压缩效率。实验结果表明,与已有的算法相比,该方法减少了测试应用的时间,提高了数据的压缩率。

A new scheme for core based System-on-a-Chip （SoC） test compression was presented. All the test vectors belonging to distinct test sets were partially overlapped to form overlapped vectors as short as possible. Variable-Run-Length （VRL） coding was utilized to further compress the result overlapped test vectors, Due to the fact that test application time is proportional to the length of the overlapped vector, except that the length of the overlapped vector is far smaller than the sum of the length of the original individual test vectors, minimal test application time can be obtained. Compression ratio was maximized through VRL coding. Experimental results indicate that the proposed method achieves reduced test application time and significant compression rate in comparison with the existing methods.