摘要
提出了一种采用流水线采样输入的开关电容型∑-△调制器的实现方法,该方法充分利用了时钟的每一时刻。用此方法设计的∑-△调制器来样速率可提高30%。实验表明,这种方法是完全可取的。
A technique to implement a switched capacitor sigma-delta modulator by using pipelined sampling input is described , which makes full use of every moment of the clock. The sampling rate of the device designed with this method can be increased by 30%. Results from simulation show the proposed technique is preferable.
出处
《微电子学》
CAS
CSCD
北大核心
1997年第4期224-227,共4页
Microelectronics
关键词
模拟集成电路
A/D转换器
调制器
流水线采样
Analog IC . Analog-to-digital converter , Modulator .Pipelined sampling EEACC 1265H. 1250