期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

精度可配置DCT及其VLSI设计 被引量：2

Precision Reconfigurable DCT Architecture and Its VLSI Design
下载PDF
导出
摘要 利用离散余弦变换(DCT)能量分布的特性,提出一种精度可配置的DCT及其VLSI结构.根据不同的变换精度需求,通过选择DCT基向量局部最优的分布式算法展开精度,实现了变换精度损失与功耗减少的优化处理;同时对DCT基向量采用正则有符号数(canonical signed digit,CSD)编码,减少了整体电路的硬件资源开销.模拟和综合后的结果表明,该结构适合图像视频等要求低功耗、实时处理领域的可配置性应用. A precision reconfigurable discrete cosine transform （DCT） architecture was proposed in this paper. Using the character of energy distribution of the DCT matrix after 2D DCT operation, we selected the local best distributed arithmetic （DA） precision of DCT bases, which can achieve considerable power reduction in DCT operation with minimum image quality degradation. By representing the DCT bases with canonical signed digit （CSD） also reduce the overall hardware overhead. Implementation and simulation results show that the architecture was suitable for image video compression and transmission applications.
作者 李振伟 彭思龙 王强
机构地区 中国科学院自动化研究所国家专用集成电路设计工程技术研究中心
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2008年第3期384-389,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 国家科技支撑计划重点项目(2006BAK07B04) 中国科学院青年科技创新基金(DG07J01).
关键词 离散余弦变换 可配置 分布式算法 超大规模集成电路 discrete cosine transform reconfigurable distributed arithmetie VLSI
分类号 TN492 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

  • 1Yu S, Swartziander E E. DCT implementation with distributed arithmetic [J]. IEEE Transactions on Computers, 2001, 50 (9): 985-991.
  • 2Fanucci L, Saponara S. Data driven VLSI computation for low power DCT-based coding [C] .Proceedings of the 9th International Conference on Electronics, Circuit, Systems, Dubrovnik Croatia, 2002 : 541-544.
  • 3Shams A M, Chidanandan A, Pan W, et al. NEDA: a lowpower high-performance DCT architecture [J]. IEEE Transactions on Signal Processing, 2006, 54(3) : 955-964.
  • 4Chidanandan A, Bayoumi M. Area efficient NEDA architecture for the 1-D DCT/IDCT [ C].Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, Toulouse, 2006:944-947.
  • 5黎铁军,王爱平,李思昆.一种基于Wallace树的分散式DCT/IDCT体系结构[J].国防科技大学学报,2006,28(1):68-72. 被引量：2
  • 6Banerjee N, Karakonstantis G, Roy K. Process variation tolerant low power DCT architecture [C].Proceedings of Design, Automation and Test in Europe Conference and Exhibition, Nice France, 2007:630-635.
  • 7Park J, Roy K. A low power reconfigurable DCT architecture to trade off image quality for computational complexity [C] .Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, Montreal, 2004:17-20.
  • 8Sinha A, Wang A, Chandrakasan A. Energy scalable system design [J]. IEEE Transactions on VLSI Systems, 2002, 10 (2) : 135-145.
  • 9IEEE Std 1180-1190-1990 IEEE standard specifications for the implementations of 8 × 8 inverse discrete cosine transform [S].

二级参考文献8

  • 1Rao K R,Hwang J J.Techniques and Standards for Image,Video and Audio Coding.Englewood Cliffs[M].NJ:Prentice-Hall,1996.
  • 2Madisetti A,Wilson A N.A 100MHz 2-D 8×8 DCT/IDCT Processor for HDTV Applications[J].IEEE Trans.on Video Technology,1995,5(2):158-164.
  • 3Cho N I,Lee S U.DCT Algorithms for VLSI Parallel Implementation[J].IEEE Trans.on ASSP.,1990,38(1):121-127.
  • 4Chang T S,Kung C S,Jen C W.A Simple Processor Core Design for DCT/IDCT[J].IEEE Trans.on CSVT,2000,10(3):439-447.
  • 5洪明吉.[D].台湾逢甲大学自动控制工程学系,2001.
  • 6Guo J I,Liu C M,Jen C W.The Efficient Memory-based VLSI Arrays for DFT and DCT[J].IEEE Trans.on CAS-II,1992,39(10):723-733.
  • 7Sun K H.Design and Implementation of a Module Generator for Low Power Multipliers[D].Master's Thesis,Division of Electronics Systems,Depart.Of Electrical Engineering,Linkoping Univ.,Sweden,Sept.25,2003.
  • 8IEEE Standard Specifications for the Implementations of 8×8 Inverse Discrete Cosine Transform[S].IEEE Std.:1180-1190.

共引文献1

同被引文献14

  • 1王进军,田泽,马小龙,刘宁宁,张强.基于逻辑努力的CMOS串行传输链延迟时间的优化分析与模拟[J].微电子学与计算机,2006,23(12):182-185. 被引量：1
  • 2金钊.Logical Effort理论在电路设计中的应用[J].现代电子技术,2007,30(2):189-191. 被引量：1
  • 3Lin C T,Yu Y C,Van L D.Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2008,16(8):1058-1071.
  • 4Tell E,Seger O,Liu D K.A converged hardware solution for FFT,DCT and Walsh transform[C] //Proceedings of the 7th International Symposium on Signal Processing and its Applications,Paris,2003:609-612.
  • 5Sansaloni T,Pérez-Pascual A,Torres V,et al.Efficient pipeline FFT processors for WLAN MIMO-OFDM systems[J].Electronics Letters,2005,41(19):1043-1044.
  • 6Li X J,Lai Z S,Cui J M.A low power and small area FFT processor for OFDM demodulator[J].IEEE Transactions on Consumer Electronics,2007,53(2):274-277.
  • 7Ahsan M,Elahi E,Farooqi W A.Superscalar power efficient fast fourier transform FFT architecture[C] //Proceedings of the 2nd IEEE International Conference on Computer,Control & Communication,Karachi,2009:1-4.
  • 8Li M,Novo D,Bougard B,et al.Generic multiphase software pipelined partial FFT on instruction level parallel architectures[J].IEEE Transactions on Signal Processing,2009,57(4):1604-1615.
  • 9Franchetti F,Kral S,Lorenz J,et al.Efficient utilization of SIMD extensions[J].Proceedings of the IEEE,2005,93(2):409-425.
  • 10Frigo M,Johnson S G.The design and implementation of FFTW3[J].Proceedings of the IEEE,2005,93(2):216-231.

引证文献2

二级引证文献1

计算机辅助设计与图形学学报
2008年 第3期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部