一种改进Turbo码译码器的FPGA设计与实现

Design and implementation of an improved Turbo decoder based on FPGA

提出了一种基于MAX-Log-MAP算法的更有效减小译码延时的方法,通过并行计算前向状态度量和后向状态度量,将半次迭代译码延时缩短一半,而译码性能没有损失,同时也减小了硬件实现中的时序控制复杂度。仿真表明,该方法有效降低了译码的延时,并且性能没有损失,具有较高的实用价值。

Base on MAX-Log-MAP algorithm, by parallel computing the forward state metric and backward metric, this paper presented a more powerful decoding scheme which could reduce the total latency of a half-iteration to half without loss in coding performance. At the same time, the difficulty of time sequence control were reduced. Finally, the simulation showed that the plan effectively decreases the latency of a half-iteration without loss in coding performance. Thus, this plan has a lot of practical value.