关于条形测试的组装技术(英文)

Assembly Concerns For Test in Strip

在过去的几年中,许多世界领先的半导体制造厂家及组装测试分包商开始了在形成完整的器件或封装体之前对引线框架、条形及板形器件的测试。类似的BIST,DFT和所有用途的更高水平的并行测试仪的测试技术的进展,将加速矩阵及条形测试的趋势。由于更多的制造厂家采用了条形测试技术,从而需要更高的生产效率和灵活性,以应对金属引线框架器件增加成本的压力和接触最新式的芯片尺寸封装几何形状难题的双重挑战。另外,新的组装特性必须考虑到它们与实现条形测试适用性的关系。分析了条形测试方面的组装方法。首先个简短的概述了为何条形测试随着实际条形测试仪器的研究情况正变得更加流行的原因,对类似的条形及基板结构、密度和几何形状等组装特性进行了讨论,强调了它们对一些不同器件类型,封装和组装特性最终测试效果的影响。

Over the last few years, many of the world＇s leading semiconductor manufacturers and assembly and test subcontractors have begun testing packaged devices in lead frame, strip or panel format prior to device or package singulation. Test technology advances such as BIST, DFT and higher parallel testers for all applications will accelerate this trend to matrix or strip testing. As more manufacturers adopt strip testing, greater throughput and flexibility will be required to deal with the dual challenges of increasing cost pressure for metal lead frame devices and the difficulties of contacting the geometries of the latest generation of chip scale packaging. Additionally, new assembly parameters must be considered as they relate to suitability to implement strip testing. This paper examines the implications of assembly methodology on strip testing. First a short overview of why strip testing is becoming more prevalent followed by case studies of actual strip test mplementations. Assembly characteristics such as strip or substrate construction, density and geometry are discussed, emphasizing their effects on overall final test efficiency for several different device types, packages and assembly parameters.