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从SOC到NOC的集成电路设计技术发展 被引量:10

From SOC to NOC:Development of IC Design Technology
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摘要 遵循摩尔定律的预言,半导体集成电路工艺技术持续高速向深亚微米工艺发展,大规模集成电路设计技术是发展过程中需要解决的关键问题。基于片上总线的SOC设计技术解决了大规模集成电路的设计难点,但是片上总线的应用带来了可扩展性差、平均通信效率低等问题。近几年研究提出全新的集成电路体系结构NOC,是将计算机网络技术移植到芯片设计中,从体系结构上彻底解决了SOC设计技术存在的问题。因此,NOC将成为集成电路下一代主流设计技术。 According to Moore's law, VLSI design is the key technology to the development of semiconductor IC towards deep submicron. SOC (system on chip) design technology based on bus solved some key issues of VLSI design. However, it has some disadvantages, such as poor scalability and lower communication efficiency, etc. A new architecture NOC (network on chip) is proposed recent years, in which bus interconnection for chip is replaced by computer network interconnection. And it will overcome the disadvantage of SOC thoroughly and become a mainstream design technology for the next generation integrated circuit.
作者 孟李林
出处 《半导体技术》 CAS CSCD 北大核心 2008年第3期190-192,共3页 Semiconductor Technology
基金 国家自然科学基金资助项目(90607008)
关键词 集成电路 片上系统 片上总线 片上网络 IC SOC bus-on-chip network on chip
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参考文献3

  • 1GUERRIER P, GREINER A. A generic architecture for onchip packet-switched [ C ] //Proc of Design Automation and Test in Europe Conf and Exhibition. Paris, France, 2000: 250-256.
  • 2HEMANI A, JANTSCH A, KUMAR S, et al. Network on chip : an architecture for billion transistor era [C]//Proc of the IEEE Norchip Conf. Turku, Finland, 2000: 166-173.
  • 3高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4):461-466. 被引量:31

二级参考文献12

  • 1ITRS.International Technology Roadmap for Semiconductors[EB/OL].http://public.itrs.net.2003.
  • 2ITRS.International Technology Roadmap for Semiconductors[EB/OL].http://public.itrs.net.1999.
  • 3Tully J,Gordon R,Bruederle S,et al.Hype cycle for semiconductors,2004[R].Gartner research's Technical Report,2004.ID Number:G00120909:2-3.
  • 4Benini L,De Micheli G.Networks on chips:a new SoC paradigm[J].Computer,2002,35(1):70-78.
  • 5Jerraya A,Wolf W,eds.Multiprocessor systems-on-chips[M].San Francisco,Morgan Kaufman / Elsevier,2004.
  • 6Hemani A,Jantsch A,Kumar S,et al.Network on chip:an architecture for billion transistor era[A].Proc IEEE NorChip Conf[C].Turku,Finland.2000.166-173.
  • 7Guerrier P,Grenier A.A generic architecture for on-chip packet-switched interconnections[A].Des Autom and Test in Euro Conf[C].Paris,France.2000.250-256.
  • 8Pham D.The design and implementation of a first-gen-eration CELL processor[A].Int Sol Sta Circ Conf[C].San Francisco,CA,USA.2005.184-185.
  • 9Glossner G.The sandbridge sandblaster SB3000 multithreaded CMP platform[A].5th Int Forum Appl Spec Multi-Processor SoC[C].Relais de Margaux,France.2005.18-23.
  • 10Jantsch A,Tenhunen H.Networks on chip[M].Dordrecht:Kluwer Academic Publishers,2003.

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