伪单输入跳变测试序列的测试生成器设计

Design of test pattern generator based on pseu-SIC test sequence

为降低内建自测试电路中的功耗,在分析内建自测试低功耗设计一般方法的基础上,从提高测试向量之间相关性的角度出发,提出了一种在不损失固定型故障覆盖率前提下降低测试功耗的BIST测试生成器设计方案.该方案在原始线性反馈移位寄存器的基础上添加了简单的控制逻辑电路,从而得到一种新的伪单输入跳变测试序列,并且在基准电路上进行了实验.实验结果表明,该设计方案在降低功耗的同时可使测试的时间大大缩短.

In order to reduce the power consumption in BIST, a new BIST TPG design that can highly reduce the test power consumption without losing fixed fault coverage has been proposed through analyzing the general low power design methods and in view of enhancing the relativity between test vectors. By adding simple control logic circuit on the original LFSR, the designed generator can generate a new pseu-SIC （single input change） test sequence. The experimental results conducted on benchmark circuit show that the proposed design can greatly reduce test time and power consumption.