基于SRAM的FPGA连线资源的一种可测性设计

A design-for-test for SRAM-based FPGA interconnect testing

FPGA(Field Programmable Gate Array)中连线资源所占面积最大,结构复杂,出现故障概率大,如何减少它的测试时间以降低测试成本,是很多研究者共同的目标。本文提出在FPGA芯片内插入多条移位寄存器链,只对开关盒连线资源进行编程下载,使得开关盒连线资源的测试时间比传统方法减少99%以上,大大减少了测试时间,降低了测试的成本。

The area of interconnection is largest in FPGAs. The interconnect is complicated and apt to be faulty. Many researchers do their best to reduce the time of testing in order to reduce the cost of testing. In this paper, we propose adding several shift register chains in FPGA chip to only configure the interconnect and the configuration time is reduced over 99%.This method can check or diagnose faults in FPGA.