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Low K芯片引线键合工艺计算机仿真与参数优化 被引量：2

Computational Modeling and Process Parameter Optimization for Wire Bonding Technology on Low-K Wafers
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摘要 Low K材料具有较高的脆性,在芯片封装测试过程中容易被损坏,因而Cu/low-K的结构的引入对芯片的封装工艺提出了很大的挑战。文章中提出引线键合工艺中冲击阶段的近似数学模型,由计算机仿真结果证实该理论模型的合理性。通过对计算机仿真结果的分析得到优化的Low K芯片引线键合工艺参数设置范围,实验设计的优化结果表明本研究提出的计算机仿真优化方法是有效的。 An approximate mathematical model is proposed to characterize the impact stage of wire bonding. The computer simulation results prove the model＇s rationality in the current low K wire bonding application. The optimal process setting ranges for the current case are deduced by analyzing the simulated responses of bond ball shape. The optimized results from DOE （ design of experiment ） confirm the effectiveness of the optimization methodology presented in this study.
作者 黄卫东
机构地区 飞思卡尔半导体中国有限公司
出处 《电子与封装》 2008年第2期1-5,共5页 Electronics & Packaging
关键词 LOW K 引线键合 有限元分析 优化 low K wire bonding finite element analysis optimization
分类号 TN305.94 [电子电信—物理电子学]
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参考文献10

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同被引文献18

  • 1何田.引线键合技术的现状和发展趋势[J].电子工业专用设备,2004,33(10):12-14. 被引量：47
  • 2杜鸣,郝跃.超深亚微米集成电路的铜互连技术布线工艺与可靠性[J].西安电子科技大学学报,2005,32(1):56-59. 被引量：5
  • 3宗飞,田艳红,王春青.Cu引线超声键合动态过程有限元模拟[J].电子工艺技术,2007,28(4):187-190. 被引量：5
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  • 5LAM J C K,HUANG M Y M,NG T H,et al.Evidence of ultra-low-k dielectric material degradation and nanostructure alteration of the Cu/ultra-low-k interconnects in time-dependent dielectric breakdown failure[J].Applied Physics Letters,2013,102(2):022908-1-022908-4.
  • 6GAN C L,NG E K,CHAN B L,et al.Technical barriers and development of Cu wirebonding in nanoelectronics device packaging[J].Journal of Nanomaterials,2012,173025:1-7.
  • 7VAN D W D.Facing the challenge of designing for Cu/low-k reliability[J].Microelectronics Reliability,2007,47(12):1969-1974.
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电子与封装
2008年 第2期

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