一种32位DSP cache存储器设计

Design of the Cache Memory in A 32-bit Digital Signal Processor

在一种DSP指令cache的设计中,采用全定制的设计方法,利用0.25μm的CMOS库设计了cache存储器。利用逻辑努力和分支努力的概念优化设计了译码电路,一方面保证了译码器的速度,另一方面减小系统的功耗。并且根据正反馈原理设计了一种差分灵敏放大器,有效地减小了存储器的功耗。电路工作在100MHz的时钟频率下,读写周期的平均动态功耗为25mW。

The memory of cache in a 32-bit Digital signal Processor is designed with the design flow of custom circuit design and the library of 0.25 μm CMOS. We use the concept of logical effort and branching effort to optimize the decoder circuit design .The power of the decoder is minimized and the speed is sufficed. A kind of sence amplifier is designed in order to minish the power. The circuit works at the frequency of 100MHz, and the average power of the reading and writing period is 25mW.