用Calibre工具对FFT芯片进行物理验证

Physical Verification in FFT Layout with Calibre

FFT芯片在Astro工具中版图设计一旦完成,必须进行设计规则检查以确保版图设计的正确性。违反规则的版图设计将成为电路生产的隐患,因此,必须在sign-off之前检查出并改正。介绍了如何使用Mentor公司Calibre工具对Astro工具导出FFT芯片的GDSⅡ文件进行设计规则检查、天线规则检查、电学规则检查和版图与电路图一致性检查,并对检查中出现的问题提出相应的解决办法。

Once the layout of FFT chip is done with Astro, the DRC must be run to make sure that the layout is correct. Layouts that violate the rules may cause troubles in later circuit production. So the faults should be detected and repaired in the layout before sign - off. This paper describes how to use Calibre of Mentor to run DRC （Design Rule Check）, antenna rule check, ERC （Electrical Rule Check） and LVS （Layout Versus Schematic） in the GDSII file which is exported from Astro. The solutions to the detected faults are also presented.