一种LDPC码的构造及其编码器的FPGA实现

A Simple Design and FPGA Implementation of Low Density Parity-Check Code

本文研究了一种构造奇偶校验矩阵H的新方法,通过这种方法构造的H不含有短长度的圈。本文同时提出了一种相对高效的LDPC码的编码方法,这种基于循环移位矩阵的准循环LDPC码的设计方法既有较好的性能又有实际应用中可接受的编码复杂度。整个设计使用Verilog语言描述,并在Altera公司的Stratix器件上实现验证。

A new and simple code-design of LDPC with a minimum girth is designed in the letterpress. While a simple design based on code matrix shift of LDPC is appeared, which has better error correcting capabilities and less encode complex for FPGA implementation. All the design implemented and validated based on FPGA Stratix of Altera corporation with Verilog HDL.