基于FPGA的Turbo译码器设计

Design of the Turbo decoder with FPGA

Turbo码良好的纠错性能为众多研究者所公认,其相关理论和实现技术一直是该领域的研究热点。本文主要围绕如何用FPGA实现Turbo码译码器,介绍了Turbo码迭代译码的硬件实现算法以及流水线译码概念,并利用Altera的Flex10k10芯片实现了该译码器。性能测试实验表明,该基于FPGA实现的译码器最高速率可达到8Mbps,性能相比于理论译码器性能下降控制在0.5dB以内,具有广阔的应用前景。

It is recognized that Turbo code is one of the best correct codes,and studying the theory and implementation about turbo code is always hot. In order to present how to design the FPGA turbo decoder, this paper introduces the main implementation algorithm and the pipeline-decoding concept,and then a test decoder is constructed with an Altera Flexl0kl0. The simulations with the help of a PC show the highest speed of the decoder is more than 8Mbps and the performance loss is less 0. 5 dB than the ideal float performance,which has a good future.