期刊文献+

一种锁相环中高性能电荷泵电路 被引量:4

A High Performance Charge Pump Circuit in PLL
下载PDF
导出
摘要 设计了一种新型电荷泵电路.该电荷泵电路采用可调节共源共栅结构增大输出阻抗,具有结构简单、速度快、充放电电流匹配性好、抑制了电荷注入等特点.采用0.18μm CMOS工艺模型以及Hspice仿真工具的仿真结果显示,输出电压在0.4~1.3V之间变化时,电荷泵的充放电电流处处相等. A novel structure of charge pump circuit is presented. To enlarge the output impedance, the charge pump is implemented with Regulated-Cascade structure, which has the advantages of a simple structure, a rapid speed, a very good matching of the charge and discharge currents, and charge injection. The Hspice simulation results using 0.18μm CMOS process models show that when the output voltage is changing from 0.4V to 1.3V, the charge and discharge currents are equivalent everywhere.
出处 《微电子学与计算机》 CSCD 北大核心 2008年第3期190-192,196,共4页 Microelectronics & Computer
关键词 锁相环 电荷泵 可调节共源共栅 PLL charge pump RGC
  • 相关文献

参考文献6

  • 1Young I A. A PLL clock generator with 5 to 100MHz of lock range for microprocessors [ J ]. IEEE J. Solid - State Circuits. 1992, 27( 11 ) : 1599-1607.
  • 2Razavi B. Design of analog CMOS integrated circuits[ M] New York: McGraw- Hill, 2000.
  • 3张涛,邹雪城,刘三清,沈绪榜.锁相环中高性能电荷泵的设计[J].微电子学与计算机,2004,21(10):169-171. 被引量:5
  • 4Rhee W. Design of high performance CMOS charge pumps in phase locked loop[C]//Proc IEEE Int Symp Cire & Syst. Orlando, FL, USA, 1999:545-548.
  • 5温显光,解宁,何乐年,徐新民,孙振国.高速PLL电路中的电荷泵电路设计[J].微电子学与计算机,2004,21(12):207-209. 被引量:4
  • 6Hosticka B J. Improvement of the gain of CMOS amplifiers [J]. IEEE J. of Solkde- state Circuits. 1979,144:1111-1114.

二级参考文献11

  • 1Lee J, Kim B. A 250 MHz low jitter adaptive bandwidth PLL. Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International . 15-17 Feb. 1999:346 - 347.
  • 2Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim, Beomsup Kim. A low-noise phase-locked loop design by loop bandwidth optimization. Solid-State Circuits, IEEE Journal of, Volume: 35, Issue: 6, June 2000:807 - 815.
  • 3Behazad Razavi. Design of Analog CMOS Intergrated Circuit[M].The McGraw-Hill Companies,Inc.,2001:547-621.
  • 4Arker J F Ray, D. A 1.6-GHz CMOS PLL with on-chip loop filter. Solid-State Circuits, IEEE Journal of, Volume:33, Issue: 3 , March 1998: 337 - 343.
  • 5Yang H C, Lee L K, Co R S. A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation.Solid-State Circuits, IEEE Journal of, Volume: 32 Issue:4, April 1997:582 -586.
  • 6Gardner F. Charge-Pump Phase-Lock Loops. Communicati ons, IEEE Transactions on [legacy, pre - 1988] , Volume:28 Issue: 11 , Nov 1980:1849 -1858
  • 7Ian A Young. A PLL clock generator with 5 to 110MHz of lock range for microprocessors[J]. IEEE J. Solid-State Circuits. 1992,27(11):1599-1607.
  • 8Van Paemel M. Analysis of a charge pump PLL: a new model[J]. IEEE Trans. on coummunications. 1994, 42(7):2490-2498.
  • 9Rhee W. Design of high performance CMOS charge pumps in phase locked loop [A].Proc IEEE Iht Symp Circ&Syst.1999, 1:545-548.
  • 10Behzad Razavi. Design of analog CMOS integrated circuits[M]. The Mc-Graw Hill Companies. 2001.

共引文献7

同被引文献19

  • 1王烜,来金梅,孙承绶,章倩苓.用于高速PLL的CMOS电荷泵电路[J].复旦学报(自然科学版),2005,44(6):929-934. 被引量:13
  • 2曾健平,谢海情,晏敏,曾云.新型全差分电荷泵设计[J].微电子学与计算机,2006,23(7):134-136. 被引量:5
  • 3朱曼子,刘伯安.一种新型混合信号时钟延时锁定环电路设计[J].微电子学与计算机,2007,24(3):154-157. 被引量:3
  • 4Thompson B, Lee H- S, De Vito L M. A 300 - MHzBiCMOS serial data transceiver[J ]. IEEE Journal of Solid- state Circuits, 1994,29(3) : 185 - 192.
  • 5Lee Joonsuk, Kim Beomsup. A 250 MHz low jitter adaptive bandwidth PLL[C]//IEEE International Solid-State Circuits Conference. Korea: Taejon, 1999: 346 - 347.
  • 6Lee K, Kim S, Ahn G, et al. A CMOS serial link for fully duplexed data communication[J]. IEEE Journal of Solid- State Circuit, 1995,30(4) : 353 - 364.
  • 7Rhee W. Design of high- performance CMOS charge pumps in phaselocked loops[J]. IEEE proceedings of the International symposium on Circuits and Systems, 1999 (1) : 545 - 548.
  • 8Lee J, Keel M, Kim S. Charge pump with perfect current matching characteristics in phase- locked loops [ J ]. Electronics Letters, 2000,36(23) :1907- 1908.
  • 9Choi Y S, I-Ian D H. Gain- bossting charge pump for current matching in phase- locked loop [ J ]. IEEE Transactions on Circuits and Systems, 2006,53 (10) : 1022 - 1025.
  • 10Razavi B. Design of analog CMOS integrated circuits [M]. Beijing: Publishing house of Tsinghua University, 2005.

引证文献4

二级引证文献6

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部