可任意设定计算精度的整数除法器的VHDL设计

Design of the decimal integer divider pre-setting up precision in calculation based on VHDL

提出了十进制整数除法的VHDL设计方法。运用有限状态机,通过移位,循环减法,能高速地实现整数除法运算,并能预定计算精度。如果系统时钟为50MHz,进行10位有效位数的十进制除法,其最长运算时间为2.2μs。

This paper gives a design of the decimal integer division based on VHDL. The integer divider operates quickly by using FSM and shifting and circular subtraction. The precision in calculation can be presetting up. The running time is not exceed 2. 2 μs to carry out decimal 10 bits effective numbers integer division in 50 MHz system clock.