摘要
近年来,随着驱动IC的I/O数量日益增多,芯片I/O端的排列密度也越来越大。为了与间距日益精细的芯片I/O端相适应,COF基板的线宽/间距已经普遍降到50μm以下,尤其是某些内部引线键合(ILB)端,其线宽/间距已经减小到15μm。由于传统的减成法存在不可避免的侧蚀问题,所以用它来制作如此精细的线路存在一定难度。但是使用半加成法就能很大程度的抑制侧蚀现象,它更适合于制作非常精细的线路。文章中,介绍以铜箔厚度仅有2μm的溅射型挠性覆铜板为原材料,采用半加成法制作了最小线宽/间距分别为50μm/50μm和30μm/30μm的精细线路基板。在半加成法的差分蚀刻工艺中,选用硫酸/双氧水蚀刻液来蚀刻去除基材铜,而不是选用常用的盐酸/氯化铜蚀刻液。结果表明,半加成法具有很好的蚀刻性能,其制作出的线路横截面非常接近矩形。即使基板的线宽/间距由50μm/50μm下降到30μm/30μm,线路的横截面依然非常理想,并没有出现向梯形变化的趋势。同时,由于半加成法所需的蚀刻时间非常短,它能很好的保持线宽,使其与设计尺寸一致。
In recent years, following the driver IC＇s I/O numbers are becoming higher, the density of IC＇s bμmps is becoming greater. For suiting these fine pitch bumps, the width/space of COF substrate is smaller than 50μm commonly and especially some width/space of ILB （Inner Line Bonding） has decreased to 15μm. Because of the unavoidable side etching, it is difficult to produce these fine lines by conventional subtractive process. The semiadditive process is more suitable for forming finer pattern because it is able to inhibit side etching greatly. In this paper, we have used sputtered FCCL with 2μm copper layer to produce two kinds of fine line substrates which are 50μm/50μm and 30μm/30μm by semi-additive process. In flash etching of the semi-additive process, we made use of not HCl/CuCl2 etchant but H2SO4/H2O2 etchant to etch the base copper. The semi-additive process has a good etching performance and the section of lines formed by it closely resemble rectangles. Even the width/space decreased from 50μm/50μm to 30μm/30μm, the section of pattern formed by semi-additive process is also ideal, and doesn＇t become trapeziform.At the same time, because the etching time in semi-additive process is very short, it leads to a better conductc, r width retention. So the width/space is closed to the design size.
出处
《印制电路信息》
2008年第3期29-32,共4页
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