摘要
随着集成电路设计规模的不断增大,设计验证工作越来越困难。介绍IEEE新标准SystemVerilog语言中用于验证的随机约束、功能覆盖率、断言技术和利用面向对象思想构建验证平台的一般方法。这些方法能极大提高芯片设计的效率,降低芯片设计的风险,减轻测试工程师的负担。
With the increasing of IC design scale, the verification becomes more and more difficult. This paper presents an IEEE new standard SystemVerilog language with constrained- random,assertion, functional coverage technologies in verification,and introduces the method of using Object Oriented Programming （OOP） thinking to build verification platform. These technologies promote the efficiency of chip design extremely, reduce the chip design risks and the test engineers＇ burdens.
出处
《现代电子技术》
2008年第6期8-11,共4页
Modern Electronics Technique
