摘要
在分析TDI CCD器件驱动时序关系的基础上,设计了积分时间和级数分别可调的驱动时序发生器。作为卫星上的有效载荷,TDI CCD成像系统可以根据不同的光照条件及探测分辨率的需求,选择不同的积分时间和级数,提高成像系统的灵敏度和信噪比。选用现场可编程门阵列(FPGA)作为硬件设计平台,使用VHDL语言对驱动时序发生器进行硬件描述,采用QuartusⅡ对所设计的驱动时序发生器进行了仿真。系统测试结果表明,所研制的驱动时序发生器可以满足高分辨率TDI CCD相机的驱动要求。
Based on the analyse of its driving schedules in detail, the driving schedule generator with simultaneously tunable integration time and series is designed for time delay and integration charge coupled device(TDI CCD) camera. As a load of satellite, TDI CCD camera can select different integration time and series to improve sensitivity and SNR, according to different illumination and exploration resolution requirements. Field programmable gates array(FPGA)has been chosen as the hardware design platform, then the driving schedule generator has been described with VHDL. The designed generator has been successfully simulated with Quartus Ⅱ software. Experiments show that designed generator is suitable for the driving requirements of high resolutution TDI CCD cameras.
出处
《半导体光电》
CAS
CSCD
北大核心
2008年第1期117-119,共3页
Semiconductor Optoelectronics
关键词
TDI
CCD
驱动时序
积分时间
现场可编程门阵列
TDI CCD
driving schedule
integration time
field programmable gates array (FPGA)