一种并行提升小波基的设计方法与VLSI实现研究

A New Design for 9/7-Tap Wavelet Filter and Its VLSI Implementation

设计了一种具有二进制特点且消失矩为4的高性能9/7小波基,提出了其VLSI高速实现结构.该小波基的提升系数的分母均可转化为2的幂次有理数,有利于简化VLSI设计.实验结果显示,其压缩性能和CDF97小波相当;在有限位宽下,其压缩性能甚至优于CDF97.新的VLSI结构实现仅需加法和移位等简单运算,可有效地减少硬件资源,缩短关键路径.通过折叠技术和重调度技术,该硬件结构转化为一种嵌入式折叠提升结构,使得每个加法运算可并行执行,关键路径可减小至接近于一个加法器的延时,达到资源的优化利用.仿真结果表明,该硬件结构最大工作频率可达到250MHz左右,可工作的最大系统频率提高到了原来的4倍左右,与传统CDF97的4级流水线结构相比,逻辑单元数减少了约66.7%,特别适合于实时高速压缩应用.

This paper designs a new kind of lifting 9-7-tap wavelet filter with binary characteristics and presents a high speed VLSI structure for the wavelet filter. The coefficients of the lifting filters are binary numbers, so it can simplify the VLSI design. The test results for compression performances have shown that the new filter is good almost as CDF97 under PSNR. when the data has a finite accuracy, it may have a better performance than CDF97. The filter can be implemented with using adders and shifters. Therefore the hardware resources can be saved and the critical path can be shortened. According to using the folding technology and the retiming technology, the architecture of the design can be transformed into a kind of embedded folding architecture which leads to the parallel computation of addition operations. So the critical path can be shortened to nearly the time of a addition operation and the utilization of the hardware resources also has a good performance. Simulation results show that the max working frequency could almost reach 250MHz which is the four times by the CDF97; The occupied logic cell is reduced by 66.7 compared with the CDF97＋4 stages pipeline. So it is especially suitable for the high speed VLSI design.