摘要
介绍了一种采用二级流水线和 ESFR 方法设计的高性能8位网络控制器芯片,给出了芯片的系统架构、特性和子模块的设计方法,芯片采用0.25 μm CMOS 工艺成功流片,最后应用这款芯片进行系统开发.
An 8-bit high performance network controller integrated circuit which adopts a two-stage pipeline and ESFR method was introduced. The architecture, features and main modules realization of the chip are given. This chip is fabricated using 0.25 μm CMOS technology and a successfully developed system application based on it is also presented.
出处
《南开大学学报(自然科学版)》
CAS
CSCD
北大核心
2007年第6期100-104,共5页
Acta Scientiarum Naturalium Universitatis Nankaiensis
基金
天津市重点科技攻关项目(06YFGZGX03600)