基于功能虚拟原型的验证方法

Verification Methodology Based on FVP

为解决片上系统验证和设计不能同步、系统级验证效率低下的问题,该文基于统一验证方法提出一种基于可演化模型的三级验证过程模型。该模型由系统级、行为级和RTL级三级功能虚拟原型演化模型构成,在不同设计阶段复用相同的系统级验证环境,可减少验证的重复工作,将其应用于设计的整个流程,可成功地实现验证和设计同步,提高验证效率。

Given the complexity of the functionality of system on chip （SOC）, one of the main challenges of current IC design is no more than verification. We implemente a functional virtual prototype （FVP） according to the blueprint of unified verification methodology to solve the synchronization between design and verification in SOC development. The FVP is based on three levels of models： system-level, behavior-level, and register transfer level （RTL）. The efficiency of verification can be improved by using FVP as a system-level model.