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单芯片高效率降压DC-DC芯片设计(英文) 被引量:1

Design of a Monolithic High-Efficiency Step-Down DC-DC Converter
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摘要 介绍了一种单芯片DC-DC转换器IC设计与电路实现,其特点是宽负载电流条件下具有较高效率。芯片的设计和仿真基于上华0.6μm双阱、混合信号CMOS工艺。芯片的工作电压范围为2~5V,可以使用于一般的电池供电设备。对提高芯片效率的方法以及效果进行了详细的讨论分析。仿真结果表明,芯片可以产生稳定的1.8V输出电压,并提供大于500mA的输出电流,而纹波电压却小于5mV。芯片可以获得93.8%的最大转换效率,而且在5~500mA的负载电流范围内,效率始终高于86.2%。 This paper presents an integrated circuit design and implementation of a monolithic I3C-I3C converter to achieve high efficiency over wide loading conditions. The converter is designed and simulated using a 0. 6 μm twin well mixed-signal CMOS process for a supply voltage range of 2-5 V, which is compatible with portable battery-operated devices. The method to improve the efficiency is discussed. Simulation results show that the converter generates an output voltage of 1.8 V while delivering up to 500mA load current with a maximum ripple of 5 mV. The converter exhibits a maximum efficiency of 93.8% and an overall efficiency above 86. 2% with the load current from 5 mA to 500 mA.
出处 《电子器件》 CAS 2008年第2期461-464,共4页 Chinese Journal of Electron Devices
关键词 电源管理 DC-DC转换器 高效率 PWM/PFM Power Management DC-DC Converter high efficiencv: PWM/PFM
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参考文献8

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