BiCMOS工艺中VNPN晶体管的优化设计

Study on the Optimization of VNPN Transistor in BiCMOS Process

BiCMOS工艺对晶体管的工艺条件设计提出了更高的要求。结合实际BiCMOS工艺,借助专业TCAD模拟软件ISE,模拟了晶体管基区注入和退火等工艺条件对VNPN晶体管的电流增益β和击穿电压BVCEO的影响,给出了优化的设计方案。在线流片结果表明优化后:晶体管β=47,[BV]CEO=9.5V,达到了低频功率晶体管的应用要求,同时保证了BiC-MOS工艺中的CMOS器件性能不变,并且工艺稳定可在线量产。因此这种优化设计是可取的。

In BiCMOS process,it is more difficult to design process condition of bipolar transistors. The effects of base region process condition on the current gain p and breakdown voltage [BV]CEO had been analyzed in virtue of the data which were simulated by TCAD ISE. Based on the analysis, it gave the optimum process condition. Finally, the fabricated wafers validated： n-p-n transistors β= 47, [BV]CEO= 9.5 V, and they satisfied technical requirements of low frequency power transistors, while the CMOS characteristics were unchanged and the steady process can be able to mass-produce. So the optimized design is feasible.