ECL结构的PFDCP设计

PFDCP Design of ECL Structure

设计了一种基于ECL结构的PFDCP。PFD电路采用传统构架,通过增加延迟单元的方法克服死区问题,延迟单元由ECL的逻辑门构成。PFD可以工作在0.15MHz到2MHz的输入频率范围之间。同时设计了一个高精度低失配的电荷泵,可以提供四种不同大小的电流。PFDCP设计和仿真采用JAZZ0.35μm的BICMOS SBC35工艺模型,电源电压5V。电路仿真结果表明PFD的死区小于30ps,CP的失配电流小于0.4%。

This paper designed a PFDCP with ECL structure. The PFD designed with convention structure can completely overcomes the dead zone problem by add the delay time unit which is designed by ECL logic unit. The operation range of this PFD is from 0.15 MHz to 2 MHz. It is also proposed an accuracy charge pump with low current dismatch which can supply four kinds of current. The design and simulation of PFD with JAZZ SBC35 BICMOS 0.35 μm process under 5 V supply voltage. The simulation results indicated that the PFD dead zone is less than 30 ps and the CP dismatch between the up currents and down currents is less than 0.4%.