期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

高性能QC-LDPC码译码器的VLSI实现 被引量：3

VLSI Implementation of High-Performance QC-LDPC Decoder
下载PDF
导出
摘要 基于改进的最小和(Min-Sum)译码算法,提出一种高速半并行准循环低密度奇偶校验(QC-LDPC)码译码器结构.设计了对数桶型移位器来传递数据,以降低译码器内部连线的复杂度;引入微指令控制技术,使译码器的硬件结构独立于具体的码率和码的规则性,可以在不改变硬件的情况下支持任意码率;采用动态功耗管理技术,译码器可以随信道好坏自动控制功耗.基于该结构实现了一个适合中国数字电视地面传输标准(GB20600—2006)系统的LDPC码译码器,在SMIC0.18μm标准CMOS工艺下综合,总面积仅为62万等效门,频率最高可达100MHz. Based on the rearranged Min-Sum decoding algorithm, a high speed partially parallel decoder architecture suited for quasi-cyclic low density parity-check （QC-LDPC） codes is proposed. A log-barrelshifter is designed to reduce complexity of interconnection. By introducing micro-code-instruction, the decoder becomes independent with certain code rate and its regularity. It can also support any code rate without any changes in hardware. To adaptively control the power consumption under different channel conditions, a dynamic power control unit is adopted. Based on proposed decoder architecture, a QC-LDPG decoder for Chinese digital television/multi-media broadcasting （DTMB） standard （GB20600-2006） system is implemented based on SMIC 0.18μm process, its frequency can be reached up to 100 MHz at the cost of 620 k gates.
作者 邓运松 申瑞 李庆 曾晓洋
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2008年第4期432-437,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 上海市科委"创新行动计划"重点项目(077062001)
关键词 QC-LDPC码译码器 高清数字电视 最小和译码算法 QC-LDPC code decoder HDTV Min-Sum decoding algorithm
分类号 TN47 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献12

  • 1Gallager R G. Low-density parity-check codes [J]. IRE Transactions on Information Theory, 1962, 8(1) : 21-28
  • 2Fossorier M P C. Quasi-cyclic low-density parity-check codes from circulant permutation matrices [J]. IEEE Transactions on Information Theory, 2004, 50(8) : 1788-1793
  • 3Li Z, Kumar B V K V. A class of good quasi-cyclic low-density parity check codes based on progressive edge growth graph[ C] // Proceedings of the 38th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2004: 1990- 1994
  • 4Chen L, Xu J, Djurdjevie I, et al. Near-Shannon-limit quasicyclic low-density parity-cheek codes [J]. IEEE Transactions on Communications, 2004, 52(7): 1038-1042
  • 5Kienle F, Brack T, Wehn N. A synthesizable IP core for DVBS2 LDPC code decoding [ C ] //Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Munich, 2005:100-105
  • 6陈赟,曾晓洋,林一帆,向波,邓运松.符合DTMB标准的非规则码LDPC解码器VLSI设计[J].通信学报,2007,28(8):61-66. 被引量：7
  • 7乔华,管武,董明科,等.LDPC码高速译码器的设计与实现[J].北京大学学报(自然科学版)网络版(预印本),2007,2(2):pkuxbw2007018
  • 8Howland C, Blanksby A. A 220mW 1Gb/s 1024-bit rate-1/2 low-density parity check code decoder[ C] //Proceedings of IEEE 2001 Custom Integrated Circuits Conference, San Diego, CA, 2001: 293-296
  • 9Urard P, Yeo E, Paumier L, et al. A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes[ C] // Proceedings of 2005 IEEE International Solid-State Circuits Conference, San Francisco, 2005:446-447
  • 10Chen J, Fossorier M. Near optimun universal belief propagation based decoding of low-density parity check codes [J]. IEEE Transactions on Communications, 2002, 50(3): 406-414

二级参考文献6

  • 1YEO E,PAKZAD P,NIKOLI? B,et al.High throughput low-density parity-check decoder architectures[A].Proc IEEE ICCT2001[C].2001.3019-3024.
  • 2MANSOUR M M,SHANBHAG N R.A 1.6Gbit/s 2048-bit programmable and code-rate tunable LDPC decoder chip[A].Proc International Symposium on Turbo Codes and Related Topics (ISTC'03)[C].Brest,France,2003.137-140.
  • 3SHIMIZU K,ISHIKAWA T,TOGAWA N T.Power-efficient LDPC decoder architecture based on accelerated message-passing schedule[J].IEEE Transactions on Fundamentals of Electronics,Communications and Computer Sciences,2006,e89a(12):3602-3612.
  • 4BLANKSBY A J,HOWLAND C J.A 690-mW 1-Gbit/s 1024-b,rate-1/2 low-density parity-check code ecoder[J].IEEE Journal of olid-State Circuits,2002,37 (2):404-412.
  • 5数字电视地面广播传输系统帧结构、信道编码和调制[S].中国国家标准,2006.
  • 6GALLAGER R G.Low-density parity-check codes[EB/OL].http:// justice.mit.edu/people/gallager.html.

共引文献6

同被引文献34

  • 1徐华.LDPC码相关技术研究[J].微电子学与计算机,2005,22(3):178-180. 被引量：8
  • 2himizu K, Ishikawa T, Togawa N,et al. Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm [ C ]. Proceedings 2005 IEEE International Conference on Computer Design, Oct, 2005,503-510.
  • 3Zhang Y, Wang Z, Parhi K K. Efficient high-speed quasieyclic LDPC decoder architecture[C]. Proceedings 2004 Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers,Nov,2004, 1:540-544.
  • 4Frame structure,channel coding and modulation for digital televison terreswial broadcasting system[ S]. Chinese Standard, Issued 2006 ( GB 20600-2006).
  • 5Zhao C, Yuan J, Lin X, et al. Improvement of shuffled iterative decoding [ C ]. 2006 Information Theory Workshop, Oct. 2006, 114-116.
  • 6Pmbhaker A, Narayanan K. A memory efficient serial LDPC decoder architecture[ C]. Proceedings 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, Mar,2005, 5: 41-44.
  • 7Darabiha A, Carusone A C, Kschischang F R. Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity [C]. 2005 IEEE International Symposium on Circuits and Systems, May, 2005, 5:5194-5197.
  • 8GuiUoud F, Boutillon E, Touseh J, et al. Generic description and synthesis of LDPC decoders[ J]. 2007 IEEE Transactions on Communications, Nov. 2007,55:2084-2091.
  • 9Fanucci L, Rovini M, Llnsalata N E,et al. High-throughput multirate decoding of structured low-density parity-check code[ J]. 2005 The Institute of Electronics, Information and Communication Engineers, Dec,2005, E88-A:3539-3547.
  • 10Wang Z, Cui Z. A memory efficient partially parallel decoder architecture for QC-LDPC codes [ C ]. 2005 Conference Record of the Thirty-Ninth Asilomar Conference on Signals, Systems and Computers, Oct, 2005,729-733.

引证文献3

二级引证文献1

计算机辅助设计与图形学学报
2008年 第4期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部