MB-OFDM UWB系统中高吞吐率Viterbi译码器的实现

Implementation of a High Throughput Viterbi Decoder For MB-OFDM UWB System

提出了一种用于MB-OFDM UWB系统的高吞吐率低功耗Viterbi译码器结构.该结构利用基4蝶形单元的对称性,降低了Viterbi译码器的实现复杂度.采用SMIC0.13μm CMOS工艺设计并实现了该译码器,在时钟频率为240MHz时,它的最大数据吞吐率为480Mb/s,功耗为135mW.在加性高斯白噪声信道下,它的误码率十分接近理论仿真值.该译码器可用于MB-OFDM UWB系统以及其他高吞吐率低功耗的通信系统中.

In this paper, an architecture for high throughput and low power Viterbi decoder to be used in MB-OFDM UWB system is presented. The architecture, which exploits the symmetry of the radix-4 butterfly, reduces the implementation complexity of the Viterbi decoder, The decoder has been designed and implemented in SMIC 0.13μm CMOS process. The results show that maximum data rate of the decoder is 480Mb/s while clock is 240 MHz, the core power is 135mW, and the bit error rote （BER） is close to that of theory simulation result in AWGN channel. The proposed Viterbi decoder can be applied to MB-OFDM UWB system and other communication systems that need high throughput and low power.