一种开环流水线A/D转换器的系统仿真

Behavioral Simulation of Open-Loop Architecture Pipeline ADC

介绍了一种开环(Open-Loop)流水线结构的A/D转换器的行为级仿真.通过对系统结构的分析,对影响系统性能的主要参数以及非线性因素进行了深入研究,提出了对系统的主要模块进行数学建模和仿真方法.搭建了测试平台,对一个8位、250MHz采样频率的开环流水线结构A/D转换器进行了理想情况仿真,验证了系统结构,并通过对加入非理想因素后的系统仿真,得出一组满足实际系统设计要求的性能指标.

This paper introduces a behavioral simulation of a pipeline ADC which open loop architecture is adopted. A behavioral model is developed and simulated in MATLAB/SIMULINK. The parameters that affect the operation of basic ADC blocks are investigated and various non-idealities in an open loop architecture ADC, such as S/H bandwidth limitation, clock jitter, comparator offset, and interpolator gain mismatch, are analyzed. The results aid the design of open loop pipeline ADCs by providing a comprehensive set of design specifications that must be satisfied by each building block.