16×16快速乘法器的设计与实现

16×16 High-Speed Multiplier Design & Implementation

为得到高性能的乘法器,本设计通过改进的Booth算法产生部分积,用一种Wallace树结构压缩部分积,并使用减少符号位填充和减少尾部0填充两种方法有效地减小了部分积压缩器的面积,最终通过超前进位加法器组得到乘积结果.采用SMIC0.18μm工艺库,由DC(DesignCompiler)综合,时间延迟可达到4.62ns,面积为23837μm2.

To get a high-performance multiplier, this paper presents a design, which generates partial products by modified Booth algorithm, compresses them rasing a Wallace tree structure and gets the final product with a CLA array. We optimize the compressor by means of reducing the amount of symbol padding, and reducing amount of padding ＂0＂ behind addends. Using the SMIC 0.18μm process, the synthesis result of this design by DC （Design Compiler） shows that the delay can be reduced to 4.62ns and the area is 23 837μm^2.