摘要
分析了非同步采样对谐波测量精度的影响,提出采用数字锁相环来同步被测信号的方法。数字锁相环电路采用VHDL语言和可编程逻辑器件设计实现,并用MAX+plusⅡ软件进行仿真。仿真和测试结果表明,所设计的数字锁相环可以很好地跟踪被测信号,如果模值K设为1,当跟踪至180ms时,频率误差仅为0.01Hz。
The impact of asynchronous sampling for the accuracy of harmonic measurement is analyzed in this paper. Aiming at it ,the digital phase locked Logic （DPLL） is proposed to synchronize the tested signal. The circuits of DPLL are realized with VHDL and Programmable Logic Devices （PLD） and simulated with MAX＋plus Ⅱ . The result of simulation and test shows that the DPLL is good for tracking the tested signal with a frequency error of only 0.01Hz at 180ms when the value of K is set ＇ 1 ＇ .
出处
《电子技术应用》
北大核心
2008年第4期51-52,62,共3页
Application of Electronic Technique
基金
湖南省教育厅资助项目:基于FPGA和小波神经网络的电力系统暂态过程电气参数测量方法研究
07C087
关键词
数字锁相环
谐波检测
可编程逻辑器件
digital phase lock logic
harmonic measurement
programmable logic device
