期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

频率综合器中低功耗高速多模分频器设计的“时间借用”方法 被引量：1

A "Time Reuse" Technique for Design of a Low-Power,High-Speed Multi-Modulus Divider in a Frequency Synthesizer
下载PDF
导出
摘要 提出一种基于"时间借用"方法的相位切换型多模高速分频器,新型的相位切换控制策略有效地减少相位切换控制环路的延时,使得多模分频器在较低的电源电压下仍能在较高的输入频率下工作,同时获得最大可分频模数.本文设计的多模分频器采用0.35μm标准CMOS工艺流片.测试结果表明,该多模分频器能够在2.5V电源电压下对2.4GHz输入信号进行48到64分频,所消耗的最大功耗仅为4.85mW,与近来报道的CMOS多模分频器相比,进一步降低了功耗速度比. A low power,continuous phase-switching multi-modulus divider is proposed based on the ＂time reuse＂ method. The novel phase-switching control strategy significantly reduces the delay of the phase-switching control loop so that the multi-modulus divider can work with higher input frequency and obtain the maximum modulus for a low power supply. According to the measurement resuits,this multi-modulus divider can divide the 2, 4GHz input frequency by 48 up to 64 for a minimum power supply voltage of 2.5V in a 0.35μm CMOS process. The maximum power dissipation is only 4.85mW. Compared with other CMOS multi-modulus dividers reported recently,our design demonstrates a considerable improvement in .the power-to-speed ratio.
作者 袁泉 杨海钢 董方源 钟伦贵
机构地区 中国科学院电子学研究所
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第4期794-799,共6页 半导体学报（英文版）
关键词 多模分频器 相位切换 低功耗 时间借用 multi-modulus divider phase-switching low power time reuse
分类号 TN772 [电子电信—电路与系统]
  • 相关文献

参考文献11

  • 1Pottie G J, Kaiser W J. Wireless integrated network sensors. Commun ACM, 2000 :51.
  • 2Lin T H,Kaiser W J, Pottie G J. Integrated low-power communication system design for wireless sensor networks. IEEE Communications Magazine, 2004:142.
  • 3Fang S J, Bellaouar A, Lee S T, et al. An image-rejection down- converter for low-IF receivers. IEEE Trans Microw Theory Tech,2005,53(2):478.
  • 4Ravi A, Banerjee G, Bishop R E, et al. 10GHz, 20mW, fast loc- king,adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesizer in a 0.18μm digital CMOS process. Symposium on VLSI Circuits,2003:181.
  • 5Lam C, Razavi B. A 2.6-GHz/5. 2-GHz frequency synthesizer in 0. 4-μm CMOS technology, IEEE J Solid-State Circuits, 2000,35:788.
  • 6Theil D, Durdodt C, Hanke A,et al. A fully integrated CMOS frequency synthesizer for Bluetooth. Proc IEEE Radio Frequency Integrated Circuits Symp,2001:103.
  • 7Craninckx J, Steyaert M. A 1.75GHz/3V dual-modulus divide-by- 128/129 prescaler in 0.7μm CMOS. IEEE J Solid-State Circuits, 1996,31:890.
  • 8Krishnapura N, Kinget P R. A 5.3-GHz programmable divider for HiPerLAN in 0.25-mm CMOS. IEEE J Solid-State Circuits,2000, 35:1019.
  • 9Shu K, Sanchez-Sinencio E, Silva-Martlnez J, et al. A 2.4GHz monolithic fractional-N frequency synthesizer with robust phase- switching prescaler and loop capacitance multiplier. IEEE J Solid- State Circuits, 2003,38:866.
  • 10Craninckx J, Steyaert M. Wireless CMOS frequency synthesizer design. Boston: Kluwer Academic Publishers, 1998.

同被引文献10

  • 1KARAMV I, ROGERS J W M. A 3.5 mW fully integrated 1.8 GHz synthesizer in 0. 13-μm CMOS [C] // IEEE NEWCAS. 2006 :49-52.
  • 2PENG Y-H, LU L-H. A 16-GHz triple-modulus phaseswitching prescaler and its application to a 15-GHz frequency synthesizer in 0. 18μn CMOS [J]. IEEE Trans Microwave Theory and Techniques, 2007, 5(1): 44-51.
  • 3YU X P, DO M A, MA J G, et al. A new 5 GHz CMOS dual-modulus prescaler [C] // IEEE Circ and Syst Int Symp. 2005:5027- 5030.
  • 4YU X P, DO M A, MA J G, et al. Low power high- speed CMOS dual-modulus prescaler design with irabalanced phase-switching technique [J]. IEEE Proc Cire Dev Syst, 2005, 152(2) : 127-132.
  • 5KRISHNAPURA N, KINGET P R. A 5. 3-GH programmable divider for HiPerLAN in 0. 25-μm CMOS [J]. IEEE J Sol Sta Circ, 2000, 35(7) : 1019-1024.
  • 6SHU K, SANCHEZ-S1NENCIO E. A 5-GHz prescaler using improved phase switching [C] // Proc IEEE Int Symp Circ and Syst. 2002, 3: 85-88.
  • 7CHIEN H-M, LIN T-H, IBRAHIM B, et al. A 4 GHz fractional-N Synthesizer for IEEE 802. 11- a [C] //IEEE Symp VLSI Circ. 2004: 46-49.
  • 8MAO X-J, YANG H-Z, WANG H. New frequency divider with 8 output phases for phase switching prescaler [C]// IEEE Conf Commun Circ and Syst, 2006, 4: 2588-2591.
  • 9李志强,陈立强,张健,张海英.一种可编程的2·4GHz CMOS多模分频器(英文)[J].Journal of Semiconductors,2008,29(2):224-228. 被引量：1
  • 10周春元,李国林.基于90nm CMOS工艺的12GHz二分频器[J].微电子学,2008,38(5):670-673. 被引量：7

引证文献1

二级引证文献4

Journal of Semiconductors
2008年 第4期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部