Storus：一个二维片上网络拓扑结构

Storus:a 2D Network on Chip Topology

随着CMOS工艺集成度持续不断提高,单片多处理器正在成为高性能处理器结构的发展趋势,现有的片上总线结构已不足以满足片上系统设计的互连需求,近年来提出了片上网络这一新的互连结构,片上网络需要解决的问题有:选择合适的拓扑结构、路由算法、流控机制等等.文中为片上网络结构提供了一个新的拓扑结构Storus以及路由算法L2,并使用多种负载模式、多种流控机制对Storus与Torus结构进行模拟分析.模拟结果显示,Storus的平均路由延时约比Torus小2%～15%,使用热点负载模拟时,Storus的饱和吞吐量约为Torus结构的1.2～1.5倍.

As the integrity of CMOS growning up, single chip multiprocessor become development trend of high pertormance computer architecture, the original bus interconnection architecture cannot satisfy communication among proccors on single chip, so the researchers presented a new interconnection architecture, which is called network on chip. There,are several issues we have to concern for network on chip, e.g. how to choose appropriate network topology.routing algorithm, flow control mechanism and so on. This paper presents a new topology called Storus and a new routing algorithm called L2, this paper also uses a simulator called Popnet to analysis and compare the performance of Storus and Torus topologies. As the simulation result shows, the average latency of Storus topology is about 85%-98% of the latency of Torus, for hotspot traffic pattern, the throughput of Storus is about 1.2 - 1.5 times of one of Torus topology.