基于FPGA的全同步数字频率计的设计与实现

Implementation of a Complete Synchronization Digital Frequency Meter Based on FPGA

利用全同步频率测量原理,通过FPGA(Field Programmalbe Gata Array)芯片,运用VHDL语言编程设计一个全同步数字式频率计,消除了±1的计数误差,测频范围在DC^100 MHz,给出了各模块的VHDL设计方法和仿真波形.并且可以利用FPGA芯片构成系统板,具有较高的实用性和可靠性.

A complete synchronization digital frequency meter is designed using FPGA chip by VHDL language programming according to the complete synchronization measurement theory. It eliminates ±1 count error with an accurate frequency-measuring range of DC-100 MHz. This paper gives the design approach by VHDL and the simulation waveform of every module of the meter. A system board can be made with the FPGA chip, which has higher practicability and reliability.