BM迭代算法的循环架构设计及实现

Cycle architecture design of BM iterative algorithm and its implementation

BCH码的译码问题主要归结为一个关键方程的解决,即错误位置多项式的求解,BM迭代算法自1966年由Berlekamp-Massey提出以来经过不断改进,已经成为解决这一问题的成熟算法。提出了一种适合硬件实现的BM迭代算法的循环架构设计,并在此架构下分别实现了基于BM迭代算法和其简化算法的二元BCH(15,5)的FPGA译码器,显示出这一循环架构易于模块移植的优点。仿真结果表明:码组中任意不大于3 bit的随机错误都可以给予纠正。

Solving the key equation is the key for the decoding of BCH codes, namely finding error location polynomials, Berlekamp-Massey （BM） iterative algorithm has been improved continuously since it has been proposed in 1966, and it is a mature algorithm for solving this problem. A cycle architecture of BM iterative algorithm is improved for hardware implementation, and the decoder FPGA implementation based on BM iterative algorithm and its simplified one for a binary BCH （ 15,5 ） are investigated under the architecture. The excellent quality of module-reused by the architecture is shown, Simulation results indicate that three or less than three error bits can be corrected by the hardware implementation.