流水线ADC增益误差及电容失配对线性度的影响

Effects of Gain Error and Capacitor Mismatch on Linearity of Pipelined ADCs

流水线ADC的系统性能会受到各种误差源的影响,建立精确的误差模型对于优化系统设计具有重要意义。根据流水线ADC系统线性度指标之间的基本关系,提出了一种改进的增益误差模型,同时导出了增益误差和电容失配与残差输出的关系。Matlab仿真表明,该模型较传统增益误差模型更好地约束了开环增益;在相同有效系统精度要求下,电容失配对INL、DNL、SFDR的影响较增益误差大。

Based on the basic relationship between linearity parameters of pipelined A/D converters, an improved gain error model was presented. The relationship of gain error and capacitor mismatch with residue output was also induced. Matlab simulation showed that the model had a better constraint on open-loop gain, compared with the traditional ones, and the capacitor mismatch had a bigger effect on INL, DNL and SFDR than the gain error under the same effective resolution requirement.