一种低功耗12位30MHz流水线A／D转换器

Design of a Low Power 12-Bit 30 MHz Pipelined A/D Converter

设计了一种12位30 MHz 1.8 V流水线结构A/D转换器,该A/D转换器采用相邻级运算放大器共享技术和逐级电容缩减技术,其优点是可以大大减小芯片的功耗和面积。电路采用级联一个高性能前置采样保持单元和五个运放共享的1.5位/级MDAC,并采用栅压自举开关和动态比较器来降低功耗。结果显示,该ADC能够工作在欠采样情况下,有效输入带宽达到50 MHz。在输入频率达到奈奎斯特频率范围内,整个ADC的有效位数始终高于10.4位。电路使用TSMC0.18μm 1P6M CMOS工艺,在30 MHz全速采样频率下,电路功耗仅为68 mW。

A 12-bit 30 MHz 1. 8 V CMOS pipelined analog-to-digital converter （ADC） was presented, in which a power efficient op-amp sharing architecture between two successive stages was adopted to reduce chip area and power dissipation. The capacitor scaling approach was used for the same purpose. The ADC was cascaded with a high performance sample/hold unit and five op-amp sharing stages. Simulation result showed that the ADC could operate at under-sampling rate, with an effective input bandwidth up to 50 MHz. The ADC exhibited an effective number of bits （ENOB） above 10. 4 for input frequencies up to Nyquist rate at 30 MHz. Implemented in TSMC’s 0. 18 μm 1P6M CMOS process, the circuit had a power dissipation of only 68 mW at 30 MHz sampling frequency.