一种20mW 12位5MHz信号带宽连续时间Σ-Δ调制器

A 20 mW 12-Bit Continuous-Time Σ-Δ Modulator with 5 MHz Signal Bandwidth

在SMIC 0.18μm CMOS工艺条件下,设计了一个可应用于无线通讯和视频领域的高带宽低功耗Σ-Δ调制器。该调制器采用连续时间环路滤波器,较之传统的开关电容滤波器,连续时间滤波器可大大降低功耗。其中,积分器补偿可减小运放有限单位增益带宽的影响。换句话说,在同等速度下也可以减小功耗。另外,加法器和量化器是通过跨导单元和梯形电阻结合在一起的,能在很高的频率下很好地工作。在采样时钟为200 MHz和过采样率为20的条件下,该调制器采用单环3阶4位量化结构。Hspice仿真验证表明,调制器达到5 MHz的信号带宽和75 dB的动态范围;在1.8 V电源电压下,其总功耗为20 mW。

A wide-band low-power ∑-Δ modulator for wireless communication or video applications was designed based on SMIC＇s 0. 18 pan CMOS process. A continuous-time loop filter was used, which could greatly reduce the power consumption compared with the traditional switch-capacitor filter. The compensation for integrator could reduce the effect of the finite unit gain bandwidth of the operational amplifier. In addition, the adder and quantizer were combined through transconductance cells and resistive ladder, which could work well at high frequencies. For a clock frequency of 200 MHz and over-sampling rate of 20, a single loop structure with 3rd-order noise shaping and 4-bit quantization was adopted. Simulation results showed that this modulator had a signal bandwidth of 5 MHz and a dynamic range of 75 dB. Its overall power consumption is 20 mW at 1.8 V supply.