基于FPGA的任意相位时钟管理器的设计

Design of an Arbitrary Phase Clock Management System Based on FPGA

在通信双方为同源时钟的前提下,为保证时钟在接口处把所有数据都正确采样进来,利用Altera的综合开发平台Quartus II,实现了采样时钟相位根据输入数据相位自动调整,使采样时钟能找到最佳的采样时间来采样外来数据。任意相位时钟管理器可以产生高精度动态相位的时钟信号。

For the both sides under the homologous clock in communication, in order to ensure that all the interfaces can correctly sample the data entered, a method using Altera＇s Quartus Ⅱ integrated development platform is presented in this paper. With this method, a sampling clock phase of the system can adjust arbitrarily based on input data, and the sampling clock can find the best time to sample foreign data. Arbitrary phase clock management devices can produce high - precision dynamic phase of the clock signal.