FPGA被动并行配置控制器的研究与实现

Research and realization of a controller used for passive parallel asynchronous configuration of FPGA

为了快速方便地配置FPGA,文章提出了使用Flash存储FPGA的配置数据,再由CPLD控制Flash将存储的数据采用并行方式下载到FPGA的方法。由于Flash掉电后数据不会丢失,这样就解决了FPGA掉电易失的问题。该文给出了具体的硬件电路和软件模块的编程思路,通过仿真测试表明本设计的可行性。

In order to configure the FPGA quickly and conveniently, this paper presents a method-first downloading the program to Flash, and then downloading it to FPGA controlled by CPLD. Because no data in Flash will be lost if there is power failure,it solves the problem that the data will be lost if the power is off. A concrete hardware circuit and a programming thought for the software mod- ule are described. The simulation test proves that this design is feasible.