基于FPGA的AES加/解密算法的可重构设计

Reconfigurable Design for Encryption/Decryption of AES Based on FPGA

高级加密标准(AES)的传统实现方法是对加/解密算法进行单独设计,占用了过多的硬件资源。该文在分析AES加/解密算法机理的基础上,介绍了算法各模块的设计方法,通过分析提取了加/解密算法之间存在的共性,给出算法的可重构设计实例。通过FPGA仿真验证,该方案与传统设计方案相比,减少了资源的消耗。

According to the traditional method, the encryption/decryption of AES are designed separately, and it consumes lots of hardware resources. In this paper, on the foundation of analyzing the encryption/decryption of AES, the implementation method of each part about the algorithm is introduced. After analysis, the commonness of encryption/decryption is given, and reconfigurable design for the algorithm is presented. Simulation and validation on FPGA shows that this design can reduce the area cost greatly compared with other traditional design.